1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an erasable and programmable read only memory (EPROM) device for a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same.
2. Description of the Related Art
An EPROM is widely used in a variety of logic devices because it can electrically store and erase data, and it can retain data when power is turned off. The EPROM is a core device of a micro controller unit for controlling equipment such as a central processing unit (CPU) and remote controllers for household appliances like televisions (TVs), video, or audio devices.
An OTP cell product, which is a type of EPROM, can be developed in a short period of time by coding program data on the OTP cell directly by a user, and mass produced as a version of a mask ROM after making the product applicable to a nonvolatile memory device. An integrated circuit having a single poly OTP cell with a complete insulating gate is widely used as an EPROM transistor. A variety of technologies related to this device have been developed as disclosed, for example, in the following: WO 1999/17750, U.S. Pat. Nos. 6,399,442 and 6,421,293.
Data on a single poly OTP cell can be erased by an ultraviolet (UV) light, and one time programming by a user is possible. Therefore, it is essential to secure a cell data retention characteristic for storing data semi-permanently after one time programming by a user. Generally, the cell data retention characteristic in a single poly OTP depends on a material of an interlayer insulating film.
FIG. 1 is a cross-sectional view of a conventional single poly OTP cell used for an LDI (LCD driver IC) product. Referring to FIG. 1, a conventional single poly OTP cell 10 comprises a source region 16 and a drain region 18 separately formed on a semiconductor substrate 12. A channel region 20 is defined between the source region 16 and the drain region 18. A gate oxide film 22 is formed on the channel region 20, and a floating gate 30 is formed on the gate oxide film 22. Insulating spacers 32 are formed on both sidewalls of the floating gate 30.
The floating gate 30 and the insulating spacers 32 are completely covered by an interlayer insulating film 40, and the floating gate 30 is completely insulated by surrounding insulating films. The interlayer insulating film 40 that covers the floating gate 30 includes a silicon oxy nitride (SiON) film 42 adjacent to the floating gate 30, a high density plasma (HDP) insulating film 44, and a plasma-enhanced tetraethoxysilane (P-TEOS) insulating film 47, which are sequentially deposited.
In a conventional single poly OTP cell configuration in which the SiON film 42, the lowest insulating film of the interlayer insulating film 40, directly covers the floating gate 30, the SiON film is the main cause of leakage of charged electrons from the single poly OTP cell. That is, electrons charged in the floating gate 30, by initial programming, leak over time into the SiON film 42 that covers the floating gate 30, thereby causing a low program threshold voltage. This results in a weakening of the data retention characteristic of the OTP cell.
The data retention characteristic of the single poly OTP cell can be increased by adopting an insulating film material other than the SiON film 42. However, it is difficult to find a substitutable film material, which can secure a hot carrier injection (HCl) characteristic and an insulating characteristic required for forming a transistor in a main chip region, and that is formed at the same level as the SiON film on the substrate except the OTP cell region.